Subthreshold-region low-static-power-consumption capacitive logic level translator

The utility model relates to a subthreshold-region low-static-power-consumption capacitive logic level translator, which can convert low-voltage region level VddL into high-voltage region level VddH and is provided with an N-channel metal oxide semiconductor (NMOS) tube MN1, a capacitor CL, a P-channel metal oxide semiconductor (PMOS) tube MP1, a PMOS tube MP2 and a phase inverter, wherein the source of the PMOS tube MP1 is connected with the low-voltage region level VddL, and the grid, the drain and the body end of the PMOS tube MP1 are connected together and then are connected with the grid of the PMOS tube MP2; the capacitor CL is arranged between a connection point among the grid, the drain and the body end of the PMOS tube MP1 and the input end Vin of the translator; the source and the body end of the PMOS tube MP2 are connected with the high-voltage region level VddH, the drain of the PMOS tube MP2 is connected with the drain of the NMOS tube MN1, then is used as the input of the phase inverter and is c