Memory bit line segment isolation

A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being era...

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Bibliographische Detailangaben

1. Verfasser:	SIBIGTROTH JAMES M.,ESPINOR GEORGE L.,MORTON BRUCE L
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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