Memory bit line segment isolation

A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.