Method of forming semiconductor structure

Methods of fabricating a semiconductor structure including heterogeneous silicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous silicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the...

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Bibliographische Detailangaben
1. Verfasser: RIM KERN,ELLIS-MONAGHAN JOHN J.,GREENE BRIAN J.,HENSON WILLIAM K.,PURTELL ROBERT J.,WANN CLEMENT H.,WILDMAN HORATIO S
Format: Patent
Sprache:eng
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Zusammenfassung:Methods of fabricating a semiconductor structure including heterogeneous silicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous silicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different silicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second silicides or germanides are performed sequentially or in a single step.