Reduced bitline leakage current

Reduced bitline leakage current

A method for reducing power in an SRAM is achieved by applying a first voltage to all bitlines of a section of the SRAM in standby operation and applying a second voltage to all the bitlines of a section of the SRAM in normal operation. The first voltage is not greater than the second voltage.

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Bibliographische Detailangaben
1. Verfasser: WUU JOHN J.,LACHMAN JONATHAN E.,WEISS DONALD R
Format: Patent
Sprache:chi ; eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A method for reducing power in an SRAM is achieved by applying a first voltage to all bitlines of a section of the SRAM in standby operation and applying a second voltage to all the bitlines of a section of the SRAM in normal operation. The first voltage is not greater than the second voltage.