Method and module for testing integrated circuits for susceptibility to latch-up

Method and module for testing integrated circuits for susceptibility to latch-up

A test module for testing the susceptibility of an integrated circuit design to latch-up, the test module comprising a plurality of test blocks (30), connected in parallel, each test block (30) comprising an injector block (12) for applying a stress current or voltage to the respective test block (3...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CAPPON PAUL H, DE JONG PETER C, SCARPA ANDREA, SMEDES TAEDE
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Beschreibung
Zusammenfassung:A test module for testing the susceptibility of an integrated circuit design to latch-up, the test module comprising a plurality of test blocks (30), connected in parallel, each test block (30) comprising an injector block (12) for applying a stress current or voltage to the respective test block (30), and a plurality of sensor blocks (13) located at successively increasing distances from the respective injector block (12), each sensor block (13) comprising a PNPN latch-up test structure. The present invention combines the respective advantages of conventional IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.