Method of manufacturing flash memory device
A method for fabricating a NAND flash memory device is provided to broaden the surface area on a dielectric layer formed on a floating gate by forming a three-dimensional floating gate so that the surface area of the floating gate is extended. After a tunnel oxide layer(104) and a conductive layer a...
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creator | KIM NAM K.,CHOI EUN S.,OH SANG H |
description | A method for fabricating a NAND flash memory device is provided to broaden the surface area on a dielectric layer formed on a floating gate by forming a three-dimensional floating gate so that the surface area of the floating gate is extended. After a tunnel oxide layer(104) and a conductive layer are deposited on a semiconductor substrate(100) having an isolation layer, the conductive layer is etched. The conductive layer may be made of a doped polysilicon layer, W, WN, Ti, TiN, Pt, Ruby, RuO2, Ir, IrO2, or Al. After an oxide layer is formed to fill a gap between the conductive layers, a polishing process is performed until the conductive layer is exposed. After the center part of the conductive layer is etched to form a recess pattern(110), the oxide layer is removed to form a three-dimensional floating gate. After a dielectric layer is formed on the resultant structure and a polysilicon layer, a metal layer and a hard mask layer are sequentially formed, a patterning process is performed to form a contact gate. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1897256A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1897256A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1897256A3</originalsourceid><addsrcrecordid>eNrjZND2TS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIy0kszlDITc3NL6pUSEkty0xO5WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8c5-hhaW5kamZo7GhFUAAMjVKLs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of manufacturing flash memory device</title><source>esp@cenet</source><creator>KIM NAM K.,CHOI EUN S.,OH SANG H</creator><creatorcontrib>KIM NAM K.,CHOI EUN S.,OH SANG H</creatorcontrib><description>A method for fabricating a NAND flash memory device is provided to broaden the surface area on a dielectric layer formed on a floating gate by forming a three-dimensional floating gate so that the surface area of the floating gate is extended. After a tunnel oxide layer(104) and a conductive layer are deposited on a semiconductor substrate(100) having an isolation layer, the conductive layer is etched. The conductive layer may be made of a doped polysilicon layer, W, WN, Ti, TiN, Pt, Ruby, RuO2, Ir, IrO2, or Al. After an oxide layer is formed to fill a gap between the conductive layers, a polishing process is performed until the conductive layer is exposed. After the center part of the conductive layer is etched to form a recess pattern(110), the oxide layer is removed to form a three-dimensional floating gate. After a dielectric layer is formed on the resultant structure and a polysilicon layer, a metal layer and a hard mask layer are sequentially formed, a patterning process is performed to form a contact gate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070117&DB=EPODOC&CC=CN&NR=1897256A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070117&DB=EPODOC&CC=CN&NR=1897256A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM NAM K.,CHOI EUN S.,OH SANG H</creatorcontrib><title>Method of manufacturing flash memory device</title><description>A method for fabricating a NAND flash memory device is provided to broaden the surface area on a dielectric layer formed on a floating gate by forming a three-dimensional floating gate so that the surface area of the floating gate is extended. After a tunnel oxide layer(104) and a conductive layer are deposited on a semiconductor substrate(100) having an isolation layer, the conductive layer is etched. The conductive layer may be made of a doped polysilicon layer, W, WN, Ti, TiN, Pt, Ruby, RuO2, Ir, IrO2, or Al. After an oxide layer is formed to fill a gap between the conductive layers, a polishing process is performed until the conductive layer is exposed. After the center part of the conductive layer is etched to form a recess pattern(110), the oxide layer is removed to form a three-dimensional floating gate. After a dielectric layer is formed on the resultant structure and a polysilicon layer, a metal layer and a hard mask layer are sequentially formed, a patterning process is performed to form a contact gate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND2TS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIy0kszlDITc3NL6pUSEkty0xO5WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8c5-hhaW5kamZo7GhFUAAMjVKLs</recordid><startdate>20070117</startdate><enddate>20070117</enddate><creator>KIM NAM K.,CHOI EUN S.,OH SANG H</creator><scope>EVB</scope></search><sort><creationdate>20070117</creationdate><title>Method of manufacturing flash memory device</title><author>KIM NAM K.,CHOI EUN S.,OH SANG H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1897256A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM NAM K.,CHOI EUN S.,OH SANG H</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM NAM K.,CHOI EUN S.,OH SANG H</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing flash memory device</title><date>2007-01-17</date><risdate>2007</risdate><abstract>A method for fabricating a NAND flash memory device is provided to broaden the surface area on a dielectric layer formed on a floating gate by forming a three-dimensional floating gate so that the surface area of the floating gate is extended. After a tunnel oxide layer(104) and a conductive layer are deposited on a semiconductor substrate(100) having an isolation layer, the conductive layer is etched. The conductive layer may be made of a doped polysilicon layer, W, WN, Ti, TiN, Pt, Ruby, RuO2, Ir, IrO2, or Al. After an oxide layer is formed to fill a gap between the conductive layers, a polishing process is performed until the conductive layer is exposed. After the center part of the conductive layer is etched to form a recess pattern(110), the oxide layer is removed to form a three-dimensional floating gate. After a dielectric layer is formed on the resultant structure and a polysilicon layer, a metal layer and a hard mask layer are sequentially formed, a patterning process is performed to form a contact gate.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method of manufacturing flash memory device |
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