Method and system for enhancing the endurance of memory cells

An integrated circuit device (10) includes a plurality of non-volatile memory cells (V1 and V2) associated with a plurality of flag cells (F1 and F2) storing managing data. The managing data of the flag cells (F1 and F2) forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells (V1 and V2) to write new data and from which of the memory cells (V1 and V2) to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.