Silicon epitaxial wafer manufacturing method for 5íÕ power MOS tube

The related processing method for a silicon epitaxial slice used on power VDMOS tube comprises: selecting proper etching-air flow and time to decrease the concentration of impurity in the epitaxial reactor and the autodoping; for the epitaxial growth of the first layer, growing one layer of pure epitaxial layer on high-concentration substrate surface to envelop the substrate surface and edge and control the growth temperature, rate and epitaxial time, while deposing at low temperature to reduce vapor pressure of autodoping impurity and solid diffusion rate for minimal deformation; and growing the second epitaxial layer for the request on resistance and thickness.