Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model

One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process...

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Bibliographische Detailangaben
1. Verfasser: MELVIN LAWRENCE S. III,PAINTER BENJAMIN D
Format: Patent
Sprache:eng
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Zusammenfassung:One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more arbitrary (e.g., non-optimal) process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. Note that a process model (on-target, off-target, or process-sensitivity) can be represented by a multidimensional (e.g., 2-D) function. The system then identifies a problem area in the mask layout using the process-sensitivity model. Note that identifying the problem area allows it to be corrected, which improves the manufacturability of the mask layout. Moreover, using the process-sensitivity model to identify the problem area reduces the computational time required to identify the problem area.