Memory system having fast and slow data reading mechanisms

An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.