Storage circuit and method for integrating pre-decoding mechanism and selective precharging mechanism

The present invention provides a storage circuit and method for integrating pre-decoding mechanism and selective online/bit line precharging mechanism. In a memory circuit, memory cells are arranged in a matrix by ''row line-and column line'' (may also denoted as ''word line and bit line''). The invention provides a memory circuit and related method capable for independently pre-charging the row lines selectively during data accessing according to results of row pre-decoding but not pre-charging other row lines. After pre-charging, the objective memory cell is enabled to change or not to change the corresponding electric level of the connected column line according to the stored data, and a sense amplifier detects the stored data by measuring the electric level of the column line.