Gate structure of semiconductor memory device

Gate structure of semiconductor memory device

Gate structure of a semiconductor memory device comprises a gate insulation layer (31) formed on a silicon substrate (30); a gate electrode (35) on the gate insulation layer, formed by stacking a polysilicon layer (32) and a metal layer (33); and a hard mask (34) formed on the gate electrode. The hy...

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Bibliographische Detailangaben
1. Verfasser: YANG HONG-SEON,JANG SE-AUG,KIM YONG-SOO,LIM KWAN-YONG,CHO HEUNG-JAE,OH JAE-GEUN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Gate structure of a semiconductor memory device comprises a gate insulation layer (31) formed on a silicon substrate (30); a gate electrode (35) on the gate insulation layer, formed by stacking a polysilicon layer (32) and a metal layer (33); and a hard mask (34) formed on the gate electrode. The hysteresis area between the hard mask and the gate electrode layers is a size ~\ 2x10 120>C dyne/cm 2>. The hard mask includes a material selected from PESiN, PETEOS and PESiN/PETEOS.