Ferroelectric memory integrated circuit with improved reliability

Ferroelectric memory integrated circuit with improved reliability

An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sid...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WELLHAUSEN UWE, JACOB MICHAEL
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sidewall spacers are used to isolate the strap from the different layers of the capacitors. The use of spacers advantageously enables the strap to be self-aligned.