Tri-layer masking architecture for patterning dual damascene interconnects

Tri-layer masking architecture for patterning dual damascene interconnects

This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.

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Bibliographische Detailangaben
Hauptverfasser: WAETERLOOS JOOST J. M, TOWNSEND PAUL H. III, MILLS LYNNE K, STRITTMATTER RICHARD J
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.