Shift register of safety providing configuration bit

Shift register of safety providing configuration bit

The master latch (8) provides intermediate storage for a data bit (3) at a serial input (2) of the shift register cell (1). A first slave latch (10) provides intermediate storage for the data bit at the master latch. Analysis logic (13) outputs the configuration bit (6) in accordance with the data b...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KOEPPE SIEGMAR, NIEDERMEIER THOMAS, GEORGAKOS GEORG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Beschreibung
Zusammenfassung:The master latch (8) provides intermediate storage for a data bit (3) at a serial input (2) of the shift register cell (1). A first slave latch (10) provides intermediate storage for the data bit at the master latch. Analysis logic (13) outputs the configuration bit (6) in accordance with the data bits under intermediate storage in the master- and slave latches.