System and method for detecting multiple data bit errors in memory
Detection of multiple data bit errors in physically adjacent data bits in a memory boundary having a parity bit, comprising activating each of a line of a memory boundary in a memory array having the parity bit; and, directing physically adjacent data bits in an activated line to two or more parity...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | Detection of multiple data bit errors in physically adjacent data bits in a memory boundary having a parity bit, comprising activating each of a line of a memory boundary in a memory array having the parity bit; and, directing physically adjacent data bits in an activated line to two or more parity checking devices so that two or more physically adjacent data bits are not forwarded to the same one the two or more parity checking devices. |
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