Data alignment circuit in receiving channel of billion Ethernet receiver

This invention relates to a data align circuit in a giga Ether net receiver receiving channel composed of an input data array, a decider array, a 'no' generator, a guest array generator, a serial/parallel converter, an array match device and an output multipath selector, one connection way of which in the system is between the equalizer and Vilerbi decoder, the second way is to divide the module into a control part and a data channel part, the control part is connected after the equalizer, the data channel part is connected between the A/D converter and the equalizer, which aligns data on four pairs of twisted-pair lines in the receiving path so that the post decoding operates correctly. 本发明为一种千兆以太网收发器接收通道中的数据对齐电路。该电路模块由输入数据队列、判决器序列、n#-[0]发生器、猜想序列发生器、串并转换器、序列匹配器和输出多路选择器组成。其在系统中的连接方式之一，是接于数据通道的均衡器和Vilerbi译码器之间；连接方式之二，将模块分为控制部分和数据通路部分，控制部分接于均衡器之后，数据通路部分接于A/D转换器和均衡器之间。本发明可使接收通路中四对双绞线上的数据对齐，从而使后续的解码操作能够正确进行。