Digital signal processor internal storage control method for eliminating internal storage addressing waiting

The invention relates to a DSP internal memory control method of eliminating internal memory access wait, used in the design of an internal control unit in the DSP. It separates a read/write operation pipeline layer into four basic layers: a data address generating layer, an address access layer, an internal memory read layer and an internal memory write layer and designs the internal memory write operation in the forth layer in order to eliminate the internal memory access wait, as a conflict between internal memory write and read occurs, adopts a mode that the read operation first hold the control right to internal memory bus and the write content is temporarily stored into a internal memory into a write-back queue to solve the conflict, in order to enhance the DSP performance. It separates the read/write pipeline layer and adopts the method of hardware write-back queue, implementing a project of eliminating data correlation in the hardware layer and makes the development course of the DSP software completely transparent, thus making the DSP up to high master frequency and at the same time, implementing high-efficacy processing efficiency. 一种消除内存访问等待的数字信号处理器内存控制方法，用于数字信号处理器中的内存控制单元的设计。将读写操作流水层分隔成数据地址产生、地址访问、内存读及内存写四个基本层次，并且将写内存设计在第四层以消除访存等待，在发生内存写后读冲突时，采用读操作先拥有内存总线的控制权，而将写操作内容暂时存入写回队列的方式解决，以提高数字信号处理器的性能。本发明将读写操作流水层分隔并采用硬件写回队列的方法，在硬件层次上实现了一种数据相关消除的方案，且对于数字信号处理器软件开发过程完全透明，从而使得数字信号处理器在达到高主频的同时实现高效的处理效率。