Frequency locking testing circuit of lock phase ring

A testing circuit locked by frequency of phase locked loop, includes two bipartition frequency divider group containing two bipartition frequency dividers, comparison impulse generator and rising edge flip flop. The first bipartition frequency divider is used in generating the frequency division signal of input signal, the comparison impulse generator used in taking N frequency division signal outputted by first bipartion frequency divisider to do logical operation, get a comparison impulse waveform having a certain pulse width, output it to the input end of rising edge flip flop. The input signal of second bipartition frequency divider is outputted to each reset terminal of bipartition frequency divider of first divider group and the clock terminal of rising edge flip flop; the output signal of rising edge flip flop is frequency lock testing signal. This invention adopts bipartition frequency divider as basic units, in favor of reducing area of circuit board. 本发明提供一种锁相环的频率锁定检测电路，包括两个由N个两分频器组成的两分频器组，比较脉冲发生器和上升沿触发器；第一两分频器组用于产生输入信号的分频信号，其中每一个两分频器的输出分频信号都输入至比较脉冲发生器；比较脉冲发生器用于将第一两分频器组输出的N个分频信号进行逻辑运算，得到一个具有一定脉宽的比较脉冲波形，输出到上升沿触发器的输入端；第二两分频器组的输入信号经过N个分频器分频后的信号分别输出到第一分频器组各个两分频器的复位端以及上升沿触发器的时钟端；上升沿触发器的输出信号是频率锁定检测信号。本发明结构简单，并且采用两分频器作为基本单元，可靠性高，易于实现，有利于减少电路版图面积。