Polysilicon film for thin film transistor and device using the same

本发明涉及一种用于薄膜晶体管(TFT)的多晶硅薄膜和采用它制造的器件,其中,通过提供一种TFT的多晶硅薄膜、和TFT采用该多晶硅薄膜的器件,来改善TFT和器件的均匀性,该多晶硅薄膜的特征在于,对于互相垂直设置的晶体管TR1和TR2而言,最大数量的各个主要晶粒边界能够包含在有源沟道区中的概率P1和P2分别以下列表达式表示,概率P1和P2不等于0.5。表达式1:P1=(D1-(Nmax1-1)×Gs1)/Gs1;表达式2:P2=(D2-(Nmax2-1)×Gs2)/Gs2;其中D1=Llcosθ+Wlsinθ,D2=L2cosθ+W2sinθ,L1和L2是晶体管TR1和TR2的有源沟道长度,W1和...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LEE GI-LYONG, PARK CHIOE, SO YU-LONG
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:本发明涉及一种用于薄膜晶体管(TFT)的多晶硅薄膜和采用它制造的器件,其中,通过提供一种TFT的多晶硅薄膜、和TFT采用该多晶硅薄膜的器件,来改善TFT和器件的均匀性,该多晶硅薄膜的特征在于,对于互相垂直设置的晶体管TR1和TR2而言,最大数量的各个主要晶粒边界能够包含在有源沟道区中的概率P1和P2分别以下列表达式表示,概率P1和P2不等于0.5。表达式1:P1=(D1-(Nmax1-1)×Gs1)/Gs1;表达式2:P2=(D2-(Nmax2-1)×Gs2)/Gs2;其中D1=Llcosθ+Wlsinθ,D2=L2cosθ+W2sinθ,L1和L2是晶体管TR1和TR2的有源沟道长度,W1和W2是晶体管TR1和TR2的有源沟道宽度,Nmax1和Nmax2是包含在每个晶体管TR1和TR2的有源沟道区中的"主要"晶粒边界的最大数量,Gs1和Gs2是对于每个晶体管TR1和TR2的特性具有重大影响的晶粒尺寸,θ是"主要"晶粒边界对于垂直于各个晶体管TR1和TR2的有源沟道方向的方向倾斜的角度。 A polycrystalline silicon thin film used in a thin film transistor (TFT) and a device fabricated by using the same, in which the uniformity of the TFT and device are improved by providing a polycrystalline silicon thin film of a TFT characterized in that probabilities P1 and P2 in which the maximum number of respective primary crystal grain boundaries for transistors TR1 and TR2 that are arranged perpendicularly to each other can be contained in active channel regions represented as in the following expressions, respectively, and the probability P1 or P2 is not 0.5, and a device using the polycrystalline silicon thin film for the TFT. Expression 1 P1=(D1-(Nmax1-1)XGs1)/Gs1; Expression 2 P2=(D2-(Nmax2-1)XGs2)/Gs2; where D1=L1cos +W1sin , D2= L2cos +W2sin , L1 and L2 are lengths of active channels of the transistors TR1 and TR2, W1 and W2 are widths of active channels of the transistors TR1 and TR2, Nmax1 and Nmax2 are the maximum numbers of the "primary" crystal grain boundaries that can be contained in the active channel regions for each of the transistors TR1 and TR2, Gs1 and Gs2 are crystal grain sizes having a fatal effect on characteristics of each of the transistors TR1 and TR2, and is an angle in which the "primary" crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the respective transistors TR1 and TR2.