MRAM bit line word line architecture

一记忆装置，系包含形成一交错点数组的复数个位线与复数个字符线。该数组中之每个交错点上各被设置一记忆胞元。一位译码器与一字符译码器系分别被连至与该位线与字符线。一第一切换电路序列系被连至相邻的位线并沿其而配置，进以导致数组沿着此相邻位线而区分成数个区段，以致于一被缩短之规划电流路径系被提供，其降低了通过此装置之电阻。 A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device.