Buffer configuration and chip

The present invention is buffer configuration and chip thereof. Several buffers are configured on one chip, and the chip has signal source end and X output soldering pads, where X is a positive integral. The configuration method includes configuring one N-th layer buffer between two output soldering pads and connecting each output soldering pad with the corresponding N-th layer buffer; configuring one (N+1)-th layer buffer near the N-th layer buffer and connecting the N-th layer buffer with the corresponding (N+1)-th layer buffer electrically; judging whether the number of the (N+1)-th layer buffers is 1; and finishing the process if so or incrrementing N by 1 before repeating the fore said steps if not.