Low power consumption fast list by employing two stage content addressing register for comparison

The invention discloses a low power consumption fast list by employing two stage content addressing register for comparison, which comprises 64 way CAM array (64X29 bit CAM unit), 64 way SRAM array (64X22 bit SRAM unit) and final output sensitivity magnifier, wherein modified CAM unit is utilized to save the bit line conversion power consumption during pre-charging, and NNOS tube charging, PMOS discharging is utilized to reduce the voltage fluctuation on the Match line on the CAM unit. The two-level CAM can reduce power consumption substantially compared with the conventional TLB.