Microprocessor with improved instruction set system structure

A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases that involve fetch/decode units lOa-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Multi-field arithmetic/logic unit (ALU) circuitry (L1, L2, S1, S2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N1 fields, such that the multi-field result includes N1 results corresponding to the set of N1 fields. Multi-field multiplication circuitry (M1, M2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N2 fields, such that the multi-field result includes N2 results corresponding to the set of N2 fields. An instruction set architecture (ISA) is provided that is optimized for intensive numeric algorithm processing and includes a set of single instruction, multiple data (SIMD) instructions to direct the operation of the multi-field ALU circuitry and the multi-field multiplication circuitry. Non-aligned data transfer to data memory (D1, D2, 22) can be performed for byte, half word, word, and double-word data items.