LATCH CIRCUIT AND OPERATING METHOD THEREOF

A latch circuit includes a first dual interlock memory cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operably coupled to each other in a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch configured to provide an intermediate signal based on the input signal at a first node, and the second sub-latch configured to provide a second sub-latch based on the input signal at a second node. And the second sub-latch is configured to provide the same intermediate signal based on the input signal at the second node. The circuit includes a first inverter configured to logically invert the intermediate signal and provide an output signal at a third node. The circuit includes a second inverter configured to logically invert the intermediate signal and provide an output signal at a third node.