Complementary field effect transistor structure and forming method thereof
A method of forming a complementary field effect transistor structure includes forming a lower transistor in a lower wafer, where the lower transistor includes a lower source/drain region, forming a contact plug electrically connected to the lower source/drain region, and forming a metal line on the...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | A method of forming a complementary field effect transistor structure includes forming a lower transistor in a lower wafer, where the lower transistor includes a lower source/drain region, forming a contact plug electrically connected to the lower source/drain region, and forming a metal line on the lower transistor. A first portion of the metal line is vertically aligned with the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region and is vertically aligned with the second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connected to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connected to the upper transistor. The embodiment of the invention also provides a complementary field effect transistor structure.
一种形成互补场效应晶体管结构的方法包括在下部晶圆中形成下部晶体管,其中所述下部晶体 |
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