Diode large-size multi-chip superposition process structure and preparation method thereof

The invention discloses a diode large-size multi-chip superposition process structure and a preparation method thereof. The preparation method comprises the steps of product structure design, product internal structure optimization, multi-chip superposition process structure welding and epoxy sealing. The diode large-size multi-chip superposition process structure comprises a bottom-layer chip, a middle-layer chip and an upper-layer chip which are sequentially arranged from bottom to top. The invention innovatively develops and designs a diode large-size multi-chip stacking process structure and a preparation method thereof through deep research on the problem of electrical performance failure caused by easy damage of chips during multi-layer chip stacking production of the existing transient voltage suppressor TVS products. And the stability of a chip product is ensured, so that the product yield and the production efficiency are improved. 本发明公开了二极管大尺寸多芯片叠加工艺结构及其制备方法，所述制备方法包括产品结构设计、产品内部结构优化、多芯片叠加工艺结构焊接、环氧密封；