Computing system performing duty cycle regulator training and duty cycle regulator training method thereof

A training method of a memory device that adjusts an eye window of a data signal in response to a duty cycle regulator (DCA) code includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180 DEG with respect to a reference internal clock signal, and selecting a second DCA code corresponding to a second internal clock signal having a phase difference of 180 DEG with respect to the reference internal clock signal; and performing a second training operation that selects a second DCA code and a third DCA code corresponding to a second internal clock signal and a third internal clock signal, respectively, the second internal clock signal and the third internal clock signal having a phase difference of 90 DEG and 270 DEG with respect to the reference internal clock signal. In a first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in a second training operation,