Circuit conversion method, latch circuit and C-element circuit

A circuit conversion method according to one embodiment of the present disclosure includes: setting a processing target path in an asynchronous logic circuit; a first process for determining whether a glitch will occur in each of the plurality of logical units in the process target path; and a second process for performing a conversion process for converting the at least one logic unit, which is determined to be glitched in the first process, into at least one glitch suppression logic unit, the at least one glitch suppression logic unit performs the same logical operation as the at least one logic unit and is capable of suppressing glitches; and a third process for determining, after the second process, whether a burr will occur in a downstream circuit of the process target path. 根据本公开内容的一个实施例的电路转换方法包括：在异步逻辑电路中设定处理目标路径；用于确定在处理目标路径中的多个逻辑单元当中的每一个逻辑单元中是否将发生毛刺的第一处理；用于实施转换处理的第二处理，所述转换处理将在第一处理中被确定将发生毛刺的至少一个逻辑单元转换为至少一个毛刺抑制逻辑单元，所述至少一个毛刺抑制逻辑单元实施与所述至少一个逻辑单元完全相同的逻辑运算并且能够抑制毛刺；以及用于在第二处理之后确定在处理目标路径的下游电路中是否将发生毛刺的第三处理。