Device for generating high-frequency clock

The invention relates to a device for generating a high frequency clock 303, comprising a controller 311, a first FLL or PLL regulation loop 323, a fixed frequency reference clock oscillator 1101, an input signal 308, a frequency divider ratio calculator 1110 and a measurement device 509. The first FLL or PLL regulation loop 323 has a first frequency divider 520. A fixed frequency reference clock oscillator 1101 generates a reference clock 306. A measuring device 509 measures a reference signal occasionally occurring in the input signal 308 and determines a relevant effective measurement value 517. A frequency divider (520) divides the high-frequency clock (303) into the frequency of a divided high-frequency clock (521) at a division ratio and into an auxiliary clock (1112) at a second division ratio. The frequency divider ratio calculator 1110 determines a measured value of the auxiliary clock 1112 and compares the effective measured value 517 with the measured value of the auxiliary clock 1112, and thereby