Packaging structure and packaging method of flip chip

The invention discloses a packaging structure and a packaging method of a flip chip. The packaging structure of the flip chip comprises a carrier plate; the at least two metal connecting pieces penetrate through the carrier plate and form bonding pads on the two sides of the carrier plate; the chip...

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Hauptverfasser: LEI YUN, LIANG DUIJIAN, SONG GUANQIANG, ZHAO WEI, JIANG JING
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Sprache:chi ; eng
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creator LEI YUN
LIANG DUIJIAN
SONG GUANQIANG
ZHAO WEI
JIANG JING
description The invention discloses a packaging structure and a packaging method of a flip chip. The packaging structure of the flip chip comprises a carrier plate; the at least two metal connecting pieces penetrate through the carrier plate and form bonding pads on the two sides of the carrier plate; the chip is welded on the bonding pad on one side of the metal connecting piece; wherein a dam is formed between the two adjacent bonding pads on the other side far away from the chip, so as to separate the two adjacent bonding pads; and the packaging layer is arranged on one side, close to the chip, of the carrier plate and wraps and packages the chip. Through the mode, the risks of bridge cutoff, bottom windowing deviation of the packaging structure and the like when the packaging structure is installed on the substrate after packaging is completed are avoided, the problems of short circuit and the like caused by tin connection between pins of the packaging structure of the flip chip are solved, and the requirements of sm
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN118676069A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN118676069A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN118676069A3</originalsourceid><addsrcrecordid>eNrjZDANSEzOTkzPzEtXKC4pKk0uKS1KVUjMS1EogIvnppZk5Kco5KcppOVkFigkZ2QW8DCwpiXmFKfyQmluBkU31xBnD93Ugvz41GKg3tS81JJ4Zz9DQwszczMDM0tHY2LUAABXmS0H</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packaging structure and packaging method of flip chip</title><source>esp@cenet</source><creator>LEI YUN ; LIANG DUIJIAN ; SONG GUANQIANG ; ZHAO WEI ; JIANG JING</creator><creatorcontrib>LEI YUN ; LIANG DUIJIAN ; SONG GUANQIANG ; ZHAO WEI ; JIANG JING</creatorcontrib><description>The invention discloses a packaging structure and a packaging method of a flip chip. The packaging structure of the flip chip comprises a carrier plate; the at least two metal connecting pieces penetrate through the carrier plate and form bonding pads on the two sides of the carrier plate; the chip is welded on the bonding pad on one side of the metal connecting piece; wherein a dam is formed between the two adjacent bonding pads on the other side far away from the chip, so as to separate the two adjacent bonding pads; and the packaging layer is arranged on one side, close to the chip, of the carrier plate and wraps and packages the chip. Through the mode, the risks of bridge cutoff, bottom windowing deviation of the packaging structure and the like when the packaging structure is installed on the substrate after packaging is completed are avoided, the problems of short circuit and the like caused by tin connection between pins of the packaging structure of the flip chip are solved, and the requirements of sm</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240920&amp;DB=EPODOC&amp;CC=CN&amp;NR=118676069A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240920&amp;DB=EPODOC&amp;CC=CN&amp;NR=118676069A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEI YUN</creatorcontrib><creatorcontrib>LIANG DUIJIAN</creatorcontrib><creatorcontrib>SONG GUANQIANG</creatorcontrib><creatorcontrib>ZHAO WEI</creatorcontrib><creatorcontrib>JIANG JING</creatorcontrib><title>Packaging structure and packaging method of flip chip</title><description>The invention discloses a packaging structure and a packaging method of a flip chip. The packaging structure of the flip chip comprises a carrier plate; the at least two metal connecting pieces penetrate through the carrier plate and form bonding pads on the two sides of the carrier plate; the chip is welded on the bonding pad on one side of the metal connecting piece; wherein a dam is formed between the two adjacent bonding pads on the other side far away from the chip, so as to separate the two adjacent bonding pads; and the packaging layer is arranged on one side, close to the chip, of the carrier plate and wraps and packages the chip. Through the mode, the risks of bridge cutoff, bottom windowing deviation of the packaging structure and the like when the packaging structure is installed on the substrate after packaging is completed are avoided, the problems of short circuit and the like caused by tin connection between pins of the packaging structure of the flip chip are solved, and the requirements of sm</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDANSEzOTkzPzEtXKC4pKk0uKS1KVUjMS1EogIvnppZk5Kco5KcppOVkFigkZ2QW8DCwpiXmFKfyQmluBkU31xBnD93Ugvz41GKg3tS81JJ4Zz9DQwszczMDM0tHY2LUAABXmS0H</recordid><startdate>20240920</startdate><enddate>20240920</enddate><creator>LEI YUN</creator><creator>LIANG DUIJIAN</creator><creator>SONG GUANQIANG</creator><creator>ZHAO WEI</creator><creator>JIANG JING</creator><scope>EVB</scope></search><sort><creationdate>20240920</creationdate><title>Packaging structure and packaging method of flip chip</title><author>LEI YUN ; LIANG DUIJIAN ; SONG GUANQIANG ; ZHAO WEI ; JIANG JING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118676069A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEI YUN</creatorcontrib><creatorcontrib>LIANG DUIJIAN</creatorcontrib><creatorcontrib>SONG GUANQIANG</creatorcontrib><creatorcontrib>ZHAO WEI</creatorcontrib><creatorcontrib>JIANG JING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEI YUN</au><au>LIANG DUIJIAN</au><au>SONG GUANQIANG</au><au>ZHAO WEI</au><au>JIANG JING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packaging structure and packaging method of flip chip</title><date>2024-09-20</date><risdate>2024</risdate><abstract>The invention discloses a packaging structure and a packaging method of a flip chip. The packaging structure of the flip chip comprises a carrier plate; the at least two metal connecting pieces penetrate through the carrier plate and form bonding pads on the two sides of the carrier plate; the chip is welded on the bonding pad on one side of the metal connecting piece; wherein a dam is formed between the two adjacent bonding pads on the other side far away from the chip, so as to separate the two adjacent bonding pads; and the packaging layer is arranged on one side, close to the chip, of the carrier plate and wraps and packages the chip. Through the mode, the risks of bridge cutoff, bottom windowing deviation of the packaging structure and the like when the packaging structure is installed on the substrate after packaging is completed are avoided, the problems of short circuit and the like caused by tin connection between pins of the packaging structure of the flip chip are solved, and the requirements of sm</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Packaging structure and packaging method of flip chip
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T16%3A10%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEI%20YUN&rft.date=2024-09-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN118676069A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true