Method of forming semiconductor package and method of forming plurality of semiconductor packages
Methods of forming a semiconductor package and methods of forming a plurality of semiconductor packages are provided. A method of forming a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, wherein a major surface of the semiconductor die faces awa...
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creator | GOH SOON LOCK SAMSON PENG LEE SWEE KAH ZHANG ZHIZHAO CHEE HONG LEE BU PEILUAN |
description | Methods of forming a semiconductor package and methods of forming a plurality of semiconductor packages are provided. A method of forming a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, wherein a major surface of the semiconductor die faces away from the substrate; forming a vertical interconnect element on the main surface of the semiconductor die; forming an encapsulant on the substrate that encapsulates the semiconductor die; exposing the vertical interconnect element at an upper surface of the encapsulant; forming a first stage metal disk on an upper surface of the encapsulant in contact with the exposed vertical interconnect element; and forming a structured metal region on the upper surface of the encapsulant, where forming the structured metal region includes structuring the first stage metal disk.
提供了形成半导体封装的方法和形成多个半导体封装的方法。形成半导体封装的方法包括:提供基板;将半导体管芯安装在基板上,其中半导体管芯的主表面背向基板;在半导体管芯的主表面上形成垂直互连元件;在基板上形成密封半导体管芯的密封剂;在密封剂的上表面处暴露垂直互连元件;在密封剂的上表面上形成与暴露的垂直互连元件 |
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提供了形成半导体封装的方法和形成多个半导体封装的方法。形成半导体封装的方法包括:提供基板;将半导体管芯安装在基板上,其中半导体管芯的主表面背向基板;在半导体管芯的主表面上形成垂直互连元件;在基板上形成密封半导体管芯的密封剂;在密封剂的上表面处暴露垂直互连元件;在密封剂的上表面上形成与暴露的垂直互连元件</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240920&DB=EPODOC&CC=CN&NR=118676005A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240920&DB=EPODOC&CC=CN&NR=118676005A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GOH SOON LOCK</creatorcontrib><creatorcontrib>SAMSON PENG</creatorcontrib><creatorcontrib>LEE SWEE KAH</creatorcontrib><creatorcontrib>ZHANG ZHIZHAO</creatorcontrib><creatorcontrib>CHEE HONG LEE</creatorcontrib><creatorcontrib>BU PEILUAN</creatorcontrib><title>Method of forming semiconductor package and method of forming plurality of semiconductor packages</title><description>Methods of forming a semiconductor package and methods of forming a plurality of semiconductor packages are provided. A method of forming a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, wherein a major surface of the semiconductor die faces away from the substrate; forming a vertical interconnect element on the main surface of the semiconductor die; forming an encapsulant on the substrate that encapsulates the semiconductor die; exposing the vertical interconnect element at an upper surface of the encapsulant; forming a first stage metal disk on an upper surface of the encapsulant in contact with the exposed vertical interconnect element; and forming a structured metal region on the upper surface of the encapsulant, where forming the structured metal region includes structuring the first stage metal disk.
提供了形成半导体封装的方法和形成多个半导体封装的方法。形成半导体封装的方法包括:提供基板;将半导体管芯安装在基板上,其中半导体管芯的主表面背向基板;在半导体管芯的主表面上形成垂直互连元件;在基板上形成密封半导体管芯的密封剂;在密封剂的上表面处暴露垂直互连元件;在密封剂的上表面上形成与暴露的垂直互连元件</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEj0TS3JyE9RyE9TSMsvys3MS1coTs3NTM7PSylNLskvUihITM5OTE9VSMxLUcjFUFuQU1qUmJNZUgkSxKqxmIeBNS0xpziVF0pzMyi6uYY4e-imFuTHpxYDlaXmpZbEO_sZGlqYmZsZGJg6GhOjBgBBSD4z</recordid><startdate>20240920</startdate><enddate>20240920</enddate><creator>GOH SOON LOCK</creator><creator>SAMSON PENG</creator><creator>LEE SWEE KAH</creator><creator>ZHANG ZHIZHAO</creator><creator>CHEE HONG LEE</creator><creator>BU PEILUAN</creator><scope>EVB</scope></search><sort><creationdate>20240920</creationdate><title>Method of forming semiconductor package and method of forming plurality of semiconductor packages</title><author>GOH SOON LOCK ; SAMSON PENG ; LEE SWEE KAH ; ZHANG ZHIZHAO ; CHEE HONG LEE ; BU PEILUAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118676005A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GOH SOON LOCK</creatorcontrib><creatorcontrib>SAMSON PENG</creatorcontrib><creatorcontrib>LEE SWEE KAH</creatorcontrib><creatorcontrib>ZHANG ZHIZHAO</creatorcontrib><creatorcontrib>CHEE HONG LEE</creatorcontrib><creatorcontrib>BU PEILUAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GOH SOON LOCK</au><au>SAMSON PENG</au><au>LEE SWEE KAH</au><au>ZHANG ZHIZHAO</au><au>CHEE HONG LEE</au><au>BU PEILUAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming semiconductor package and method of forming plurality of semiconductor packages</title><date>2024-09-20</date><risdate>2024</risdate><abstract>Methods of forming a semiconductor package and methods of forming a plurality of semiconductor packages are provided. A method of forming a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, wherein a major surface of the semiconductor die faces away from the substrate; forming a vertical interconnect element on the main surface of the semiconductor die; forming an encapsulant on the substrate that encapsulates the semiconductor die; exposing the vertical interconnect element at an upper surface of the encapsulant; forming a first stage metal disk on an upper surface of the encapsulant in contact with the exposed vertical interconnect element; and forming a structured metal region on the upper surface of the encapsulant, where forming the structured metal region includes structuring the first stage metal disk.
提供了形成半导体封装的方法和形成多个半导体封装的方法。形成半导体封装的方法包括:提供基板;将半导体管芯安装在基板上,其中半导体管芯的主表面背向基板;在半导体管芯的主表面上形成垂直互连元件;在基板上形成密封半导体管芯的密封剂;在密封剂的上表面处暴露垂直互连元件;在密封剂的上表面上形成与暴露的垂直互连元件</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method of forming semiconductor package and method of forming plurality of semiconductor packages |
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