MEMORY CELL AND SEMICONDUCTOR DEVICE

The memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions forming a first pull-down transistor and a first pull-up transistor, respectively. A second gate structure engages the first and second active regions forming a second pull-down transistor and a second pull-up transistor, respectively. The memory cell also includes a first source/drain contact via electrically coupled to the first and second pull-down transistors, a second source/drain contact via electrically coupled to the first and second pull-up transistors, a first gate contact electrically coupled to the first gate structure, and a second gate contact electrically coupled to the second gate structure. An area of one of the first and second source/drain contact vias is greater than an area of any one of the first and second gate contacts in a plan view of the memory cell. The embodiment of the invention also provides a semiconductor device. 存储