Data latch circuit, semiconductor device, and semiconductor memory device

Data latch circuit, semiconductor device, and semiconductor memory device

The invention provides a data latch circuit capable of reducing circuit area, a semiconductor device, and a semiconductor memory device. According to one embodiment, a data latch circuit includes a first circuit and a second circuit. And a first circuit in which a first transistor of a first conduct...

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Hauptverfasser: OZAKI TAKUYA, SAKURAI KIYOFUMI, HIGASHITSUJI TEPPEI, KITSUKA EIJI, WATANABE TOSHIFUMI
Format: Patent
Sprache:chi ; eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator OZAKI TAKUYA
SAKURAI KIYOFUMI
HIGASHITSUJI TEPPEI
KITSUKA EIJI
WATANABE TOSHIFUMI
description The invention provides a data latch circuit capable of reducing circuit area, a semiconductor device, and a semiconductor memory device. According to one embodiment, a data latch circuit includes a first circuit and a second circuit. And a first circuit in which a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type are connected in series, the first circuit being capable of holding a first logic value. And a second circuit in which a third transistor of the first conductivity type and a fourth transistor of the second conductivity type are connected in series, the second circuit being capable of holding a second logic value obtained by inverting the first logic value. The data latch circuit can apply either a first voltage or a second voltage different from the first voltage to the back gates of the first transistor and the third transistor, and can apply a third voltage to the sources of the first transistor and the th
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN118629465A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN118629465A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN118629465A3</originalsourceid><addsrcrecordid>eNrjZPB0SSxJVMhJLEnOUEjOLEouzSzRUShOzc1Mzs9LKU0uyS9SSEkty0xO1VFIzEtBk8lNzc0vqoQq4GFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYWZkaWJmamjsbEqAEA1hU0vw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data latch circuit, semiconductor device, and semiconductor memory device</title><source>esp@cenet</source><creator>OZAKI TAKUYA ; SAKURAI KIYOFUMI ; HIGASHITSUJI TEPPEI ; KITSUKA EIJI ; WATANABE TOSHIFUMI</creator><creatorcontrib>OZAKI TAKUYA ; SAKURAI KIYOFUMI ; HIGASHITSUJI TEPPEI ; KITSUKA EIJI ; WATANABE TOSHIFUMI</creatorcontrib><description>The invention provides a data latch circuit capable of reducing circuit area, a semiconductor device, and a semiconductor memory device. According to one embodiment, a data latch circuit includes a first circuit and a second circuit. And a first circuit in which a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type are connected in series, the first circuit being capable of holding a first logic value. And a second circuit in which a third transistor of the first conductivity type and a fourth transistor of the second conductivity type are connected in series, the second circuit being capable of holding a second logic value obtained by inverting the first logic value. The data latch circuit can apply either a first voltage or a second voltage different from the first voltage to the back gates of the first transistor and the third transistor, and can apply a third voltage to the sources of the first transistor and the th</description><language>chi ; eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240910&amp;DB=EPODOC&amp;CC=CN&amp;NR=118629465A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240910&amp;DB=EPODOC&amp;CC=CN&amp;NR=118629465A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OZAKI TAKUYA</creatorcontrib><creatorcontrib>SAKURAI KIYOFUMI</creatorcontrib><creatorcontrib>HIGASHITSUJI TEPPEI</creatorcontrib><creatorcontrib>KITSUKA EIJI</creatorcontrib><creatorcontrib>WATANABE TOSHIFUMI</creatorcontrib><title>Data latch circuit, semiconductor device, and semiconductor memory device</title><description>The invention provides a data latch circuit capable of reducing circuit area, a semiconductor device, and a semiconductor memory device. According to one embodiment, a data latch circuit includes a first circuit and a second circuit. And a first circuit in which a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type are connected in series, the first circuit being capable of holding a first logic value. And a second circuit in which a third transistor of the first conductivity type and a fourth transistor of the second conductivity type are connected in series, the second circuit being capable of holding a second logic value obtained by inverting the first logic value. The data latch circuit can apply either a first voltage or a second voltage different from the first voltage to the back gates of the first transistor and the third transistor, and can apply a third voltage to the sources of the first transistor and the th</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB0SSxJVMhJLEnOUEjOLEouzSzRUShOzc1Mzs9LKU0uyS9SSEkty0xO1VFIzEtBk8lNzc0vqoQq4GFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYWZkaWJmamjsbEqAEA1hU0vw</recordid><startdate>20240910</startdate><enddate>20240910</enddate><creator>OZAKI TAKUYA</creator><creator>SAKURAI KIYOFUMI</creator><creator>HIGASHITSUJI TEPPEI</creator><creator>KITSUKA EIJI</creator><creator>WATANABE TOSHIFUMI</creator><scope>EVB</scope></search><sort><creationdate>20240910</creationdate><title>Data latch circuit, semiconductor device, and semiconductor memory device</title><author>OZAKI TAKUYA ; SAKURAI KIYOFUMI ; HIGASHITSUJI TEPPEI ; KITSUKA EIJI ; WATANABE TOSHIFUMI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118629465A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>OZAKI TAKUYA</creatorcontrib><creatorcontrib>SAKURAI KIYOFUMI</creatorcontrib><creatorcontrib>HIGASHITSUJI TEPPEI</creatorcontrib><creatorcontrib>KITSUKA EIJI</creatorcontrib><creatorcontrib>WATANABE TOSHIFUMI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OZAKI TAKUYA</au><au>SAKURAI KIYOFUMI</au><au>HIGASHITSUJI TEPPEI</au><au>KITSUKA EIJI</au><au>WATANABE TOSHIFUMI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data latch circuit, semiconductor device, and semiconductor memory device</title><date>2024-09-10</date><risdate>2024</risdate><abstract>The invention provides a data latch circuit capable of reducing circuit area, a semiconductor device, and a semiconductor memory device. According to one embodiment, a data latch circuit includes a first circuit and a second circuit. And a first circuit in which a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type are connected in series, the first circuit being capable of holding a first logic value. And a second circuit in which a third transistor of the first conductivity type and a fourth transistor of the second conductivity type are connected in series, the second circuit being capable of holding a second logic value obtained by inverting the first logic value. The data latch circuit can apply either a first voltage or a second voltage different from the first voltage to the back gates of the first transistor and the third transistor, and can apply a third voltage to the sources of the first transistor and the th</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title Data latch circuit, semiconductor device, and semiconductor memory device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T06%3A53%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OZAKI%20TAKUYA&rft.date=2024-09-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN118629465A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true