Data latch circuit, semiconductor device, and semiconductor memory device

The invention provides a data latch circuit capable of reducing circuit area, a semiconductor device, and a semiconductor memory device. According to one embodiment, a data latch circuit includes a first circuit and a second circuit. And a first circuit in which a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type are connected in series, the first circuit being capable of holding a first logic value. And a second circuit in which a third transistor of the first conductivity type and a fourth transistor of the second conductivity type are connected in series, the second circuit being capable of holding a second logic value obtained by inverting the first logic value. The data latch circuit can apply either a first voltage or a second voltage different from the first voltage to the back gates of the first transistor and the third transistor, and can apply a third voltage to the sources of the first transistor and the th