Low power adder circuit

The invention relates to a low power adder circuit. The circuit includes a first adder portion that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder portion that receives the first input and the second input and adds the inputs to generate a second sum. An input processor of the circuit receives a first input and a second input, determines whether a relationship between the first input and the second input satisfies a set of conditions, and selects a high power mode of the adder circuit or a low power mode of the adder circuit using the determined relationship between the first input and the second input. When the relationship satisfies the set of conditions, the high power mode is selected and routes the first and second inputs to a second adder portion. 本发明涉及低功率加法器电路。该电路包括第一加法器部分，该第一加法器部分接收第一输入和第二输入并且将所述输入相加以生成第一和。该电路也包括第二加法器部分，该第二加法器部分接收第一输入和第二输入并且将所述输入相加以生成第二和。该电路的输入处理器接收第一输入和第二输入，确定在第一输入与第二输入之间的关系是否满足条件集，并且使用所确定的在第一输入与第二输入之间的关