Preparation method of low-on-resistance planar gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

The invention provides a preparation method of a low-on-resistance planar gate silicon carbide VDMOS. The preparation method comprises the following steps: epitaxially growing on a silicon carbide substrate to form a first drift layer; performing ion implantation on the first drift layer to form a current sharing layer and a second drift layer; forming a barrier layer on the upper part of the second drift layer, and performing etching and ion implantation to form a well region; forming an N-type source region and a P-type source region; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; forming a source metal layer; re-forming a barrier layer, overturning the device, re-forming a barrier region on the silicon carbide substrate, etching the barrier region to form a through hole, etching the silicon carbide substrate, depositing metal, and forming a metal filling struc