Time division multiplexing IO communication bus

The invention, which relates to the technical field of industrial automation, discloses a time division multiplexing IO communication bus comprising a CPU module and an IO module. The CPU module and the IO module are in communication connection through an SPI bus; wherein the SPI bus comprises an MOSI data line, an MISO data line and a CLK clock line; the CPU module is in communication connection with the SPI bus; the IO module comprises a CPLD controller and an MCU controller. The MOSI data line and the MISO data line are both connected with the MCU controller, the CLK clock line is connected with the CPLD controller, and the CPLD controller is connected with a chip selection pin of the MCU controller; and the CPLD controller is used for outputting chip selection signals to the MCU controller based on the number of the clock signals sent by the CLK clock line. The technical problem that an existing IO communication bus chip selection signal occupies multiple ports of a controller and occupies multiple data l