Processing circuit and operating method thereof
A method of performing a last shift multiply-accumulate (MAC) process. The processing circuitry may multiply the first input by a first bit of the second input to obtain a first intermediate output. The processing circuitry may multiply the third input by the first bit of the fourth input to obtain...
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| creator | ZHAO WEICHENG KE RUIYANG MORI YOKI FUJIWARA HIDEHIRO |
| description | A method of performing a last shift multiply-accumulate (MAC) process. The processing circuitry may multiply the first input by a first bit of the second input to obtain a first intermediate output. The processing circuitry may multiply the third input by the first bit of the fourth input to obtain a second intermediate output. The processing circuitry may sum the first sum and the second intermediate output to obtain a first sum. The processing circuit may multiply the first input by a second bit of the second input to obtain a third intermediate output. The processing circuit may multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output. The processing circuit may sum the third intermediate output and the fourth intermediate output to obtain a second sum. The processing circuitry may generate an output by accumulating the first sum and the second sum. The embodiment of the invention relates to a processing circuit and an operation method thereof.
一种执行最后移位乘法累加(MAC)处理 |
| format | Patent |
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一种执行最后移位乘法累加(MAC)处理</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Processing circuit and operating method thereof |
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