Master-slave optimized address writing method and device

The invention discloses a host-slave optimized address writing method and device. The method comprises the steps that the level of a first address writing line of a first slave is lowered at a host end; delaying a first time period; sending address writing data to the bus; at the first slave end, receiving and judging whether the bus data comprises address writing data of the first slave or not; if yes, receiving bus data, extracting address writing data of the slave from the bus data, and performing address writing or address rewriting operation on a first memory of the first slave; receiving and judging whether the bus data comprises the address writing data of the second slave machine or not at the second slave machine; if yes, receiving bus data, extracting address writing data of the slave, and performing address writing or address rewriting operation on a second memory of a second slave; and sending a second response that address rewriting is completed to the bus. In the method provided by some embodime