Amplitude limiting circuit applied to high-speed comparator and working method thereof
The invention discloses an amplitude limiting circuit applied to a high-speed comparator. The amplitude limiting circuit comprises a cascode PMOS (P-channel Metal Oxide Semiconductor) tube module circuit, a cascode NMOS (N-channel Metal Oxide Semiconductor) tube module circuit, a diode D3, a diode D...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses an amplitude limiting circuit applied to a high-speed comparator. The amplitude limiting circuit comprises a cascode PMOS (P-channel Metal Oxide Semiconductor) tube module circuit, a cascode NMOS (N-channel Metal Oxide Semiconductor) tube module circuit, a diode D3, a diode D4 and a resistor R1, the positive electrode of the diode D3 is electrically connected with the negative electrode of the diode D4 through the resistor R1; the negative electrode of the diode D3 and the positive electrode of the diode D4 are jointly and electrically connected with the grid electrode of an MN9 transistor in the NMOS transistor module circuit, the two signal output ends of the PMOS transistor module circuit are electrically connected with the positive electrode and the negative electrode of the diode D3 respectively, and the two signal output ends of the NMOS transistor module circuit are electrically connected with the positive electrode and the negative electrode of the diode D4 respectively; the re |
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