Data processing method and device, chip and computer equipment

The invention discloses a data processing method and device, a chip and computer equipment, and relates to the field of computers. The method comprises the following steps: starting a timer of a cache line when the state of the cache line in the memory is changed from a non-modified state to a modified state. And when the timer of the cache line is overtime, writing the cache line back to the next-level memory. Therefore, the cache line in the modified state is monitored based on the timer of the cache line, so that the cache line cannot be kept in the modified state for a long time, and when the timer of the cache line is overtime, the cache line is written back to the next-level memory, so that the data of the cache line is backed up; the problem of data failure hidden danger of the modified cache line caused by bit inversion is effectively relieved, so that the reliability of the modified cache line is improved. 公开了数据处理方法、装置、芯片和计算机设备，涉及计算机领域。方法包括：根据存储器中缓存线的状态从非修改态变为修改态时，启动缓存线的定时器。当缓存线的定时器超时时，将缓存线写回到下一级存储器。