Overtime monitoring circuit and chip

The invention discloses an overtime monitoring circuit and a chip, and relates to the technical field of chips. The circuit comprises a state controller which is used for outputting a low-power-consumption entry counter enable signal to an entry timeout monitoring module after receiving a system low-power-consumption request signal, and outputting a low-power-consumption entry success signal to the entry timeout monitoring module when detecting that a chip successfully enters a low-power-consumption mode; the entry timeout monitoring module is used for starting timing when the low-power entry counter enable signal is received to obtain first timing time, and outputting an entry timeout monitoring reset signal to the reset module when the first timing time is greater than or equal to the low-power entry monitoring preset time and the low-power entry success signal is not received; the reset module is used for outputting an overtime monitoring reset signal to reset the chip when the overtime monitoring reset si