Memory device detecting word line path defects and method of operating same

A memory device includes a memory cell array connected to a plurality of word lines; a clock generator configured to generate a clock signal; a charge pump circuit configured to generate a voltage to be supplied to the plurality of word lines based on a clock signal; a row decoder configured to prov...

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Hauptverfasser:	BYEON DAE-SEOK, KWON TAE-HONG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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