Memory device detecting word line path defects and method of operating same

A memory device includes a memory cell array connected to a plurality of word lines; a clock generator configured to generate a clock signal; a charge pump circuit configured to generate a voltage to be supplied to the plurality of word lines based on a clock signal; a row decoder configured to provide a voltage to the selected memory block; a current generation circuit connected in parallel with a word line path through which a voltage is supplied from the charge pump circuit to the row decoder, and configured to generate a current flowing through the word line path within a reference time; and a defect detection circuit configured to detect a defect on the word line path by comparing a first count value of the clock signal counted before a reference time with a second count value of the clock signal counted after the reference time. 一种存储器设备，包括连接到多条字线的存储器单元阵列；被配置为生成时钟信号的时钟生成器；被配置为基于时钟信号生成要提供给多条字线的电压的电荷泵电路；被配置为向所选存储器块提供电压的行解码器；与字线路径并联连接的电流生成电路，电压通过该字线路径从电荷泵电路被提供给行解码器，并且该电流生成电路被配置为在参考时间内生成流经字线路径的电流；以及缺陷检测电路，被配