High bandwidth memory module architecture

A high bandwidth dual in-line memory module (HB-DIMM) includes a plurality of memory chips, a plurality of data buffer chips, and a register clock driver (RCD) circuit. The data buffer chips are coupled to the respective sets of memory chips and transfer data from the memory chips via the host bus at a data rate that is twice the data rate of the memory chips. The RCD circuit includes a host bus interface and a memory interface coupled to a plurality of memory chips. The RCD circuit implements a command received via the host bus by routing a command/address (C/A) signal to the memory chip for providing at least two independently addressable dummy channels, the RCD circuit addressing each respective dummy channel based on chip identifier (CID) bits derived from the C/A signal. 高带宽双列直插式存储器模块(HB-DIMM)包括多个存储器芯片、多个数据缓冲器芯片以及寄存器时钟驱动器(RCD)电路。数据缓冲器芯片被耦合到存储器芯片的相应集合，并且经由主机总线以存储器芯片的数据速率的两倍的数据速率从存储器芯片传输数据。该RCD电路包括主机总线接口和耦合到多个存储器芯片的存储器接口。该RCD电路通过将命令/地址(C/A)信号路由到存储器芯片以用于提供至少两个能够独立寻址的伪通道来实施经由主机总线接收的命令，该RCD电路基于从C/A信号导出的芯片标识符(