Area, cost and time efficient scan coverage improvements

The present disclosure relates to area, cost and time efficient scan coverage improvements. According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. A first input of the OR gate is coupled to a control signal, and a second input of the OR gate is coupled to uncovered functional combinatorial logic of the digital circuit. The first input of the OR gate is configured to be pulled down by a control signal in response to a configuration that sets the digital circuit to test uncovered functional combinatorial logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a test of the uncovered functional combinatorial logic to detect defects in the digital circuit. 本公开涉及面积、成本和时间有效的扫描覆盖改进。根据实施例，数字电路包括OR门和触发器。OR门包括第一输入和第二输入。OR门的第一输入耦接到控制信号，并且OR门的第二输入耦接到数字电路的未覆盖的功能组合逻辑。OR门的第一输入被配置为响应于将数字电路设置为测试未覆盖的功能组合逻辑的配置而被控制信号拉低。触发器包括耦接到OR门的输出的重置引脚或设置引脚。触发器的