Planar SiC MOSFET structure capable of reducing on-resistance

The invention discloses a planar SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure capable of reducing on-resistance, which comprises a metal source, and a metal drain, an N + substrate and an N-epitaxial layer which are sequentially stacked from bottom to top, and is characterized in that a stepped JFET region, an inverted stepped Nwell region, an inverted stepped P-type base region, a gate oxide layer, a polycrystalline silicon gate and a dielectric layer are sequentially stacked at one end of the N-epitaxial layer from bottom to top; a deep P + region and an N + source region are also arranged in the N-epitaxial layer, and a stepped terminal structure is arranged at the other end of the N-epitaxial layer; according to the invention, the problem that the on-resistance cannot be reduced due to the limitation of the square JFET on the on-resistance in the traditional plane gate structure is solved, the gate width is reduced, and the current density of the device is further increased. 本发