Semiconductor structure and forming method thereof

Self-aligned gate isolation/dicing techniques for multi-gate devices are disclosed herein. An example multi-gate device includes a first gate having a gate stack surrounding a semiconductor layer. The first gate is disposed between the first gate isolation wall and the second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, and the first sidewall is formed by the gate dielectric and the gate electrode. A gate end cap is disposed on the first sidewall. A gate cap is disposed over the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate cap. A gate contact is disposed on the first gate. The gate contact extends over the first gate isolation wall and connects the first gate to the second gate. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof. 本文公开了用于多栅极器件的自对准栅极隔离/切割技术。示例性多栅极器件包括具有围绕半导体层的栅极堆叠件的第一栅极。第一栅极设置在第一栅极隔离壁和第二栅极隔离壁之间。栅